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2.
3.
Assign the rest of the PCI pins around the package in the order that will match the add-in connector. Do not use
any of the special function pins.
Connect the PCI CLK to one of the GL input pins on the opposite side of the package.
Axcelerator and RTAX-S Families
The pins should be located around one side of the package in the order specified by the PCI specification. The pins
should be located on the lower side of the package using the bank 4 and bank 5 I/O locations.
1.
2.
3.
Locate TRDYN and IRDYN close to the routed clock inputs, but do not use these pins.
Assign the rest of the PCI pins around the package in the order that will match the add-in connector. Do not use
any of the special function pins.
Connect the PCI CLK to an HCLK input pin.
Care should be taken to minimize the number of I/O banks used; the I/O banks used for PCI signals must be set to use
PCI electrical levels that may be incompatible with other devices connected to the FPGA. When using large packages,
exercise care in making sure that the PCI track lengths can be met with the planned pinout and FPGA location on the
PCB. In some cases it may be necessary to move the PCI clock to an RCLK network to reduce the PCB track lengths.
Fusion, IGLOO/e, ProASIC3L, and ProASIC3/E Families
The pins should be located around one side of the package in the order specified by the PCI specification. Initially,
identify an I/O bank that contains the global inputs G***.
1.
2.
3.
Assign the TRDYN and IRDYN pins to, or close to, two of these global inputs.
Assign the rest of the PCI pins around the package in the order that will match the add-in connector. Leave one
spare normal I/O pin vacant close to the global pins. Do not use any of the special function pins.
For 33 MHz operation, connect the PCI CLK to a global input. For 66 MHz operation, connect the CLK to the I/
O pin left vacant close to the global inputs.
Care should be taken to minimize the number of I/O banks used; the I/O banks used for PCI signals must be set to use
PCI electrical levels that may be incompatible with other devices connected to the FPGA.
SmartFusion2
There are typically four PCI-capable banks available on most devices, that is, the MSIO banks. For example, on the
M2S050T device, Banks 1, 2, 3, and 8 support the PCI standard. However, to meet timing and to ease board layout,
130
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